- An awesome video on cartoon style animation from 3D Rendering: How To Create Toon Style Animation In Blender
- To change the size of your grid if it's dwarfed by your object scale, press the "n" key and expand the "Display" tab. Then you can increase the scale and other grid properties.
**Video Editing**

Circuit simulation can be a great tool for engineering. A free and open source software (FOSS) solution can be even better. Here are a collection of resources and notes that I'm compiling as I learn about the ideal setup.

- I would like to use a package I'm very familiar with KiCAD which is a great FOSS designed for circuit board design. It can be compatible with SPICE (Simulation Program with Integrated Circuit Emphasis), however a few configuration steps need to be executed.
- I'm following this guide to set it up: Quick Guide to Using KiCad for SPICE Simulation
- Based on recommendations, I am going with ngspice as the SPICE engine. This is responsible for actually doing the simulation calculations and processes. It can be seen as a "necessary add-on"
- I downloaded the ZIP and placed it in my Program Files folder.

- While perusing this, I decided it might be more convoluted then I may want. I may come back to it, but I am going to further explore options first.
- Also, I could not find a decent library of SPICE components, so I will need to further look into it.
- Plus, though SPICE can be powerful, in my experience I can work faster with a GUI based system

- Looking at Quite Universal Circuit Simulator (QUCS) which is FOSS and has a decent looking GUI.
- I am going to try following this fairly comprehensive tutorial: Qucs - A Tutorial
- Speed up the process by memorizing the hot keys (
*note to self: find or make a list of shortcuts*) - While messing around, I noticed that the transformer component does not appear to respond correctly when dealing with a pulse. Instead, I have to use the "mutual inductor" component.

- Speed up the process by memorizing the hot keys (
- There is a utility available for converting Qucs to KiCAD: qucs2kicad It may be worth looking into.
- Some notes on my ~20 minute trial
- It seems to be reasonably intuitive
- I like the way the simulation outputs can be displayed on the same window as the circuit (See the above figure)
- Directly export data to a PNG or CSV
- This example here shows live parameter optimization, a feature which I find to be truly useful
- Looks like It has all of the basic components I'd need for analog circuit design

- I am going to try following this fairly comprehensive tutorial: Qucs - A Tutorial

- A Decent First Tutorial: Basic Part Design Tutorial
- Hotkeys:
- Ctrl +: Zoom in
- Ctrl -: Zoom out

- Here's a great video on triads and how easy they can imitate Hollywood film scores
- How to Imitate a Whole Lot of Hollywood Film Music In Four Easy Steps
- These are easily adaptable to guitar chords... Follow the same steps, but find each next note on the higher (pitch wise) string.
- Alternatively, here are some triad shapes. They are all major; to make them minor, move the middle note up one half step (one fret)

- Initial links visited
- Wikipedia Basic Application Information
- A collection of many basic Op-Amp Circuits
- Single supply design considerations
- Instrumentation Amplifiers, single supply and specialized
- Digi-key Specialized Instrumentation Amplifier that is not 1 million dollars

- Op-Amps for Current Sensors
- Don't forget it's a good idea to design for resistor values that actual exist

Interpolation is the act of making an educated guess based on other known information. In the contents of this article, I'm going to specifically be looking at the derivation of a process to make interpolations based on a grid of 3D points. So eventually, given an input $X$ and $Y$ coordinate, we can find the interpolated Z height. This method is implemented in the Voltfolio G-Code Leveler which is mostly made to aid in PCB Leveling.

So we can start off by assuming a 2D array of points evenly spaced by $\Delta{X}$ and $\Delta{Y}$. The data at each point in the array corresponds to a measured $Z$ height. Four points $P$, $Q$, $R_I$ and $R_{II}$ define a rectangular region, that is off-set from the reference origin (IE if $P$ is $(0,0,Z)$ Then $X_{offset}$ and $Y_{offset}$ will both be 0.).

First, we have to confirm that our given point falls in the region we are looking at. Sure this seems pretty trivial, but if implemented in a program, this will have to be done. Assume a 2D arbitrary point $(X,Y)$. In order for this point to fall in the region of concern, the following inequalities must be true:

$$X_{offset} \leq X \leq (X_{offset}+\Delta{X})\\

Y_{offset} \leq Y \leq (Y_{offset}+\Delta{Y})$$

We now know that our point is in the rectangular region, however we must now find out if the point is in sub region I or II. This is important because a plane can only be constrained by 3 points. The interpolation will always uses points $P$ and $Q$, but we must determine if $R_I$ or $R_{II}$ is to be used. The point is located in sub region I if the following inequality is true. This will indicate that $R_I$ must be used for the interpolation.

$$\frac{X}{\Delta{X}} > \frac{Y}{\Delta{Y}}$$

If the above inequality is not satisfied, then the point is in sub region II, and satisfies the following relation. $R_{II}$ must be used.

$$\frac{X}{\Delta{X}} \leq \frac{Y}{\Delta{Y}}$$

Now that we have located our point, we can go on to determining Z. Let us define the following:

$$P=(X_1,Y_1,Z_1)\\

Q=(X_2,Y_2,Z_2)\\

R=(X_3,Y_3,Z_3)$$

From these three points, two vectors can be defined:

$$\vec{PQ} = <X_2-X_1, Y_2-Y_1,Z_2-Z_1>\\

\vec{PR} = <X_3-X_1, Y_3-Y_1,Z_3-Z_1>$$

Now it is possible to find the the normal vector formed by $\vec{PQ}$ and $\vec{PR}$. This can be done by carrying out the cross product:

$$\vec{n} = \vec{PQ} \times \vec{PR} =\begin{vmatrix}

\vec{i} & \vec{j} & \vec{k} \\

X_2-X_1 & Y_2-Y_1 & Z_2-Z_1 \\

X_3-X_1 & Y_3-Y_1 & Z_3-Z_1

\end{vmatrix}$$

The value of this determinate is found to be:

$$\vec{n} = (Y_2-Y_1)(Z_3-Z_1)\vec{i} + (Z_2-Z_1)(X_3-X_1)\vec{j} + (X_2-X_1)(Y_3-Y_1)\vec{k} - (Y_2-Y_1)(X_3-X_1)\vec{k} - (Z_2-Z_1)(Y_3-Y_1)\vec{i} - (X_2-X_1)(Z_3-Z_1)\vec{j}$$

It can keep things much cleaner from here on out if we develop a short hand for the $\vec{i}$, $\vec{j}$ and $\vec{k}$ parts of the above equation:

$$L = [(Y_2-Y_1)(Z_3-Z_1)-(Z_2-Z_1)(Y_3-Y_1)]\vec{i}\\

M = [(Z_2-Z_1)(X_3-X_1)-(X_2-X_1)(Z_3-Z_1)]\vec{j}\\

N = [(X_2-X_1)(Y_3-Y_1)-(Y_2-Y_1)(X_3-X_1)]\vec{i}$$

A 3D plane can now be defined given the normal vector and a point on the plane, which is assumed to be our point $(X,Y,Z)$ where $X$ and $Y$ are known values:

$$L(X-X_1)+M(Y-Y_1)+N(Z-Z_1)=0$$

Finally, solving for $Z$, we find our solution:

$$Z=\frac{-L(X-X_1)-M(Y-Y_1)}{N} - Z_1$$

Phew. Now that wasn't so bad. It's only a little bit of Calculus III, but nothing too unmanageable (or in my case, not too un-recallable). This general equation can now be used for many different interpolation purposes. Specifically for the PCB leveling problem, it allows a small amount of points to be measured in an array. Then when you need to know the $Z$ height at a point somewhere in between two recorded values, this equation can be applied and a linear extrapolated value can be found.

A fuzzy set can be defined by weights and their corresponding values. For example:

$$A = 0.1/x1+0.4/x3 +1.0/x4$$

$$B = 0.3/x1 + 0.2/x2 +0.6/x3+0.2/x4$$

Here, the first term in $A$ can be viewed as a wight of $0.1$ at point $x1$

These sets can be operated on using Zadeh's operators:

- $A^c(x)=1-A(x)$
- $(A\cup B)(x)=max \{ A(x),B(X) \}$
- $(A\cap B)(x)=min\{ A(x),B(x) \}$

So for example if we wanted to find the union (indicated by the $\cup$ symbol) of $A$ and $B$,

$$A\cup B = max \{ 0.1,0.3 \} /x1 + max \{ 0.0, 0.2 \} /x2 + max \{ 0.4,0.6 \} /x3 + max \{ 1.0,0.2 \} /x4$$

$$A\cup B = 0.3/x1 + 0.2/x2 + 0.6/x3 + 1.0/x4$$

And the intersection is:

$$A\cap B = min \{ 0.1,0.3 \} /x1 + min \{ 0.0, 0.2 \} /x2 + min \{ 0.4,0.6 \} /x3 + min \{ 1.0,0.2 \} /x4$$

$$A\cup B = 0.1/x1 + 0.0/x2 + 0.4/x3 + 0.2/x4$$

These are examples of T-Norms and T-Conorms. T-Norms and T-Conorms are basic algebraic operators that work on fuzzy sets.

The following pages are a set of content that I have prepared for a workshop that I have instructed at SVSU for 2 sessions. The topics I cover include:

- Basic schematic design
- Board construction techniques
- Routing Techniques and tools
- Conductor property calculations
- Getting boards manufactured

The workshop involves a discussion on The NI Circuit Board Design Suite, as well as a step by step design process for making a power supply circuit board. Then attendants are given a custom measurment circuit design, and are given the opportunity to apply their new skills to design a circuit board during the workshop.

__A special thanks to IEEE Student Chapter for sponsoring the event and providing lunch.__

**Basic Circuit Design**

For this workshop it is assumed you have basic experience with Multisim. That said, the skills necessary for this workshop can be acquired quickly, as Multisim is used only for layout, and a knowledge of simulation tools will not be necessary. These are skills that should get developed in regular course work.

**Concepts of Nets**

A "net" is another term for a connection or a "virtual wire." In terms of circuit theory, a net is a "node". By default nets are the red lines connecting component terminals according to your designTo make net numbers visible, right click on a blank part of the schematic, then click properties. In the Sheet visibility tab, under "Net names" click "Show all." Nets will be auto-assigned a number name, however a descriptive name can be given to the net by right clicking it > Properties > Enter in the name under "Preferred net name." Something to note below is that though V1 and R5 are not connected with a red line, they

*are*both connected to ground, which Multisim will automatically assume is the same net.*A part of a schematic showing labeled net connections***Net Properties (and how they translate to PCB)**

At the bottom of Multisim's window is a section called "Spreadsheet View" and at the very bottom are some tabs (Results, Nets, Components, etc). Click Nets to view Net Properties.*The 'Nets' tab of Multisim*

Typically, when you are doing simulations in Multisim, the net properties are not too important. But once you start designing a PCB, these properties become__very__important. In this tab, you can change the following properties of your selected net (only relevant properties are mentioned):- Trace width: This will specify the width of the trace in mil (Note 1 mil is 1/1000 inch) A larger trace width can handle a larger current
- Trace length min and max: These specify the limits of the lengths that a trace can extend. Typically you shouldn't have to enter any value in these cells, unless you are dealing with a very special noise sensitive signal where you want carefully control the electromagnetic properties (IE if the trace is acting as an antenna)
- Trace to Trace: This specifies the "Volt Spacing" between traces. This specifies the physical distance (in mil) between the selected trace and any other trace. Note that if the specified spacing for two parallel traces varies, Ultiboard will always use the larger value.
- Trace to pad: This value specifies the volt spacing between the trace and any given solder pad. As a rule of thumb, I would say it's safe to keep trace spacing the same for all spacing properties (IE Trace to Trace = Trace to Pad)
__UNLESS__the board will not be coated with solder resist. Then it is a good idea to increase the spacing from Trace to pads to prevent accidental solder bridges. The upper and lower limits can also be specified. - Trace to Via: Specifies the spacing between the trace and any given via. It's typically safe to keep this the same as the Trace to Trace spacing value.
- Trace to copper area: Specifies the distance between the trace and any given copper area (copper plane typically used for power distribution)
- Routing Layer: PCBs can consist of multiple layers. By default, Multisim will set the design to a two layer board. To increase the amount of layers, click (at the top of the window) Options > Sheet Properties > PCB and then increase the "layer pairs" number. Which layer you choose to route signals on is entirely up to you. A standard is to keep small signals on a separate layer from power signals.

**Types of components and circuits (Simulated, layout only, etc)**

There are three types of circuit components you can add in Multisim their type specifies their function in Simulation and PCB design.- Simulation and layout (model and footprint): These components can be used in your Multisim simulations because they have a SPICE code assigned to them. They can also be used in the PCB layout because they have (or will have) a footprint assigned to them. These components are colored blue.
- Simulation only (model): These components only have SPICE code, and no footprint. The components will not show up on the PCB design in Ultiboard. These components are colored black.
- Layout only (footprint): These components to not effect the simulation and are only used in PCB design. These components are colored green.
*An image demonstrating the three types of components*

**Making custom components**

The sad truth about Multisim is it doesn't have every electronic part that has ever been created. So, sometimes, you have to create a model of the component yourself! This is typically a 6 step process that starts by clicking (at the top of the window) Tools > Component Wizard.- The first screen is the "Component Information Screen" page. Here is where you name the component that you are creating, summarize its function, and select the component type. Typically, you're going to be selecting "Layout only" unless you have an intimate understanding of the part and are interested in including a SPICE model as well. I'm not going to go over that though. Click Next.
*Component Wizard - Component Information Screen* - The "Footprint Info" screen is where you will select the footprint for your component. If the component is a standard form factor, you can click "Select a footprint" > Master Database where you'll have to do some searching to find the exact form factor you are looking for. If you've already created a footprint it will be in the "Select a footprint" screen under "User Database." If you plan to make a new footprint but haven't made it yet, just type in the name of the footprint in "Footprint type", specify the number of pins on the component, and then click next. It will ask you to fill out some information about the footprint, which should be strait-forward. If you are dealing with a component with a lot of pins, consider clicking the "Multi-section component" dot, in order to split the layout representation into multiple pieces.
*Component Wizard - Enter Footprint Information Screen* - The "Symbol information" screen is where you can review the schematical symbol that Multisim generated for your part. You can edit it to any shape that might make more sense for your schematical layout. Note that changing this symbol will not change anything on the PCB layout.
*Component Wizard - Enter Symbol Information Screen* - The "Pin Parameter" page will allow you to name pins, select which section the pin is include in (if you selected the symbol to be multi-section in the previous step), the signal type, and the ERC Status (If it its connections are checked by the error checker). I typically keep the Type and ERC status at the default settings.
*Component Wizard - Set pin parameters screen* - The "Pin Mapping Screen" is where you connect the assign the schematic pins to the footprint pins. Do so by clicking the "Map Pins" button. It is sometimes safe to click the "Auto Assign" button if your symbol pin names are numeric values starting at 1. But in any other case (IE you named the pins alpha-numeric names) you are going to have to manually assign pins to one another)
*Component Wizard - Pin Mapping Screen* - The last step in the "Family Tree Selection" screen is where you can either select a family in the user data base or corporate database to save you designed component. The corporate database is for parts that might be hosted on a company server that multiple people would use.
*Component Wizard - Family Tree Selection Screen*

- The first screen is the "Component Information Screen" page. Here is where you name the component that you are creating, summarize its function, and select the component type. Typically, you're going to be selecting "Layout only" unless you have an intimate understanding of the part and are interested in including a SPICE model as well. I'm not going to go over that though. Click Next.
**Transferring designs to Ultiboard**

There are two tasks you might want to accomplish when designing transferring a design to Ultiboard.- A New Design: If the design is new, at the top of the window click Transfer > Transfer to Ultiboard > Transfer to Ultiboard 13.0. This will prompt you to create new files that will open up in Ultiboard
- Changing an Existing Design: If you make a change to the schematic, but already have a PCB design in progress, you are going to have to "Forward Annotate". To do this, click Transfer > Forward Annotate to Ultiboard > Forward Annotate to Ultiboard 13.0. You can save the net list at a revision, and then select which board file you would like to revise.

- First consider the base material
- Single Layer:

- Double Layer:
- Just add a layer of copper to the single layer

- Mutli Layer:
- Layers are usually in multiples of two, because of the manufacturing method
- "Core Layer"
- Much like the double layer board, except it utilizes thinner epoxy glass
- Double layer boards only have thick epoxy glass for rigidity

- Core Stackup

- "Core Layer"

- Layers are usually in multiples of two, because of the manufacturing method

- Dimensions:
- Manufacturers will specify normal layer thicknesses, but engineers can specify for special cases
- Thickness is controlled by adding or subtracting epoxy glass layers, or using thinner or thicker copper
- Note: Reducing epoxy glass thickness will make the board less rigid, and will decrease "volt spacing"

**Note:** **Circuit boards are not limited to 1-4 layers. In fact, some very advanced boards can be up to 100 layers!**

- Traces
- What is a trace?
- Essentially, a wire, cut into the copper part of the circuit board

- What is a trace?

- How are traces made?
- Based on a design, copper is removed from areas around traces, to make the trace electrically separate (no continuity) from the rest of the copper.
- Two methods for manufacturing:
- Milling
- Using a tiny endmill and a CNC controlled mill, material is cut out according to a sed of G-Code instructions generated from the board design file

- Chemical Etching
- A transparent sheet has an image of the board layout printed on it
- black means: keep material
- clear means: remove material

- A reaction with light, the chemical, and the copper trace take place, dissolving the copper in specified regions

- A transparent sheet has an image of the board layout printed on it

- Milling

- Vias and Through-Holes
- Vias are for connecting traces from layer to layer

- Through-holes are very similar to vias, except they end on the bottom layer with "solder pads"

- Electroplating:
- Using high precision placement and head, copper is plated on the edge of the holes drilled for vias and through-holes

- Solder Resist:
- Using a similar method to chemical etching, a photo sensitive reaction adds solder resist where specified
- Solder resist will not allow molten solder to bond with it
- It serves two purposes:
- Preventing Solder Bridges
- Insulating Traces from the rest of the world

- Multisim
- Basic Circuit Design
- Concepts of Nets
- Net Properties (and how they translate to PCB)

- Types of components and circuits (Simulated, layout only, etc)
- Making custom components
- Multisim Layout
- Ultiboard Layout (More mentioned later)
- Linking the two layouts

- Transferring designs to Ultiboard

- Basics of Circuit board construction
- Layer by layer breakdown
- How traces are made
- Electroplating
- Board stackup
- Understanding core's composition

- How Vias work
- Solder Resist

- Ultiboard
- Ratsnest and its purpose
- Setting Net Properties
- Trace Width Calculation
- Power dissipation plane
- Parallel layers
- Copper Thickness Availability
- Machinability of thicker copper

- How to use tools to calculate

- Volt Spacing
- Researching manufacturer stack ups
- Also consider capacitive coupling
- How to use tools to calculate

- Differential, or noise sensitive traces
- Parallel, same trace length

- All Net properties should be set
__before__start of design

- Trace Width Calculation
- Brief touch on complex part design
- Adjusting grid spacing and origin location and its uses
- Placing Shapes
- Working with Ultiboard is sometimes not user friendly
- 3D Data and Transfer to Solidworks

- Power Planes
- Detrimental if left ungrounded
- Can make routing easier

- Considerations on Board rigidity
- Routing
- Line tool and its uses
- Follow me tool and its uses
- Connection machine and its uses
- Via Placement
- Cost considerations of through-holes

- Routing Logic
- Ever other layer every other direction principle
- Minimize capacitive coupling

- Branching busses
- Differential pair routing
- Keep to a side idea
- Room for vias when needed

- Considerations for trace heat dissipation
- Types of corners
- 90 degrees and its detriments
- Avoiding sloppy routing (minimize trace vertices)

- Copy and pasting Routing
- Being clever with coordinate placement

- Ever other layer every other direction principle
- The Autorouter
- When and when not to use it
- Configuration for autorouting
- Layer Direction
- Importance of Net settings with autorouter

- Design Rule Check (DRC)
- What they mean
- Do not ignore them
- Board cannot be manufactured if they exist

- Net List editor
- Reverse annotation back to Multisim
- Adding parts and making design changes

- Finalizing designs
- Gerber files
- Manufacturers specifications
- Communication with manufacturer

- Revisions

The first session was attended by electrical engineering students (ranging from freshmen to senior), mechanical engineering students, and even a chemistry student. Overall my feelings tell me that the workshop was very successful, and the survey results reflect that:

- This workshop increased my skills in PCB Design: 95.7% Total Agreement
- The material was taught in an understandable manner: 97.1% Total Agreement
- The reference hand-outs were relevant and helpful: 94.3% Total Agreement
- I would attend more practical design-based workshops like this one: 98.6% Total Agreement

Here are some of the comments received regarding the workshop:

"The workshop was very well put together and I learned a lot about PCB design and the use of Multisim and Ultiboard Software. I really enjoyed it, and would love to attend workshops like this in the future.""Very well done. Good amount of time teaching and letting us work on our own.""Please do more things like this in the future. It was helpful and I enjoyed it. Shane was awesome and patient"

- Introductions: Name, Class Standing, Major
- Notes on Circuit Board Construction and Anatomy
- Talk about some existing circuit boards, and observations
- Multisim Tools for Making Custom PCBs
- Make Custom Component

- Ultiboard Basics
- Trace Width Calculations (with PCB Toolkit)
- Volt Spacing
- Make Custom Component

- Power Suppy Circuit Board Design (Step by Step)
- Lunch
- Measurment Board (On your own, or with small groups)
- Survey

**The Rat's Nest**

The first thing you'll see when you transfer a Multisim design to Ultiboard is a bunch of components connected by a "ratsnest." The ratsnest are a bunch of thin yellow lines connecting components. The purpose of these lines are to signify that a trace has not yet been routed between the two terminals. Note that these connections are only virtual, and do not represent hard-wired connections on the PCB. You can turn off the ratsnest by unchecking it in the "Design Toolbox" at the left of the screen.*Unplaced components connected by a Ratsnest***Setting Net Properties**- Trace Width Calculation

Trace width specifies how wide a trace is, which in turn specifies the maximum safe current capacity. The standards can be found on IPC-2221 (PCB Design Standards Document), and the equation can be derived from their given curves (Credit to 4PCB.com)

$$W=(\frac{Current}{k*Temp_{rise}^b})^{\frac{1}{c}}*\frac{1}{Thickness*1.378}$$

Where k = 0.024, b = 0.44 and c = 0.725 for internal layers. For external layers: k = 0.048, b = 0.44, c = 0.725. Current given in Amps, Temp rise in Deg C, Thickness in Oz.- Parallel layers

If for any reason you cannot make a trace wide enough (perhaps you can't make if fit between component pins), consider using using parallel traces of equal width, to effectively double current capacity. These parallel traces don't have to be on the same layer either. - Copper Thickness Availability

PCBs can be made with varying copper thicknesses. Using a thicker copper will allow for a smaller trace width. However there are two things that you have to note when using non-standard copper thicknesses. First, does the manufacturer you intend to use supply that thickness? The second thing to consider is; As Thickness increases, the machinablity decreases. This means that traces will have to be wider (in order for it to be possible to manufacture), and volt spacing may need to be bigger. To determine if this is an issue and how to remedy it, you're going to need to call your PCB manufacturer and ask what their capabilities are. - How to use tools to calculate

To be honest, I don't use the trace width equation given above. I'm efficient (no I am not lazy), and I use a tool called PCB Toolkit by Saturn PCB. When you first open the toolkit, there is a lot to digest. At the top, click "Conductor Properties" and take a deep breath. The top left section, and the right section is all input for the program, and the bottom left set of boxes are outputs. I'm going to discuss what I think is meaningful for this workshop. The rest are a bit technical, and with a bit of Googling, you can figure them out.- Plane Present?: If you have a whole layer that is mostly copper parallel to your trace, click "Yes" in this section. This will increase the allowable current through the trace. The reason is because you have a sheet of copper close to your trace that can act as a heat sink, which provides more surface area for heat dissipation.
- Parallel Conductors: See the above section on parallel conductors for reasons on why you would want to do this. Note that the toolkit will only provide results for 1 of the conductors. So for example, if you have 2 parallel conductors and need to handle 1A, adjust your conductor width until the current is 0.5A
- Conductor Width: Here is the main thing you want to work with. Vary this number until you have achieved the desired results in the bottom section.
- PCB Thickness: A Standard overall PCB thickness is 62 mil. You're going to have to check with your manufacturer to see what the "Stackup" or thickness of your PCB is. When in doubt for a 2 layer board, typically leave it 62 mil.
- Base Copper Weight: Copper Weight actually refers to the thickness of the copper. When it's time to get your board manufactured, you'll specify this. Copper weight relates to Copper thickness by the following equation

$$Thickness(mil) = Weight (Oz) * 1.37$$ - Conductor Layer: If your conductor is in an internal layer (for example if you have a 4 layer board) then specify it as such. You'll notice that the conductor current will drop in comparison to the External Layer alternative. That is because there is now a layer of Epoxy glass insulating the trace, and heat cannot dissipate as easily as if it were on the top of the board exposed directly to air flow. Therefore it is a good idea to put high power traces on top or bottom layers
- Temp Rise: I typically leave this value alone. This specifies how hot the trace can get above ambient before it melts (or you consider it to be too hot)
- Conductor Current: This is how much current the trace can support with out heating up to a temperature above the specified Temp Rise.
- Conductor DC Resistance: This indicates the resistance of the trace. Note that this is also highly dependent on Conductor Length. If a trace is already routed in Ultiboard, the length can be found in the "net properties tab"
- Power Dissipation: At peak current, this is how much power will be dissipated by the trace.
*The PCB Toolkit Conductor Properties Tab*

- Parallel layers
- Volt Spacing

Volt Spacing (called trace clearance in Ultiboard) is a parameter that specifies the distance between the edge of a trace and another conductor. It is called "Volt Spacing" because this distance must be big enough such that there will not be possible for an electrical arc while at the standard operating voltage.- Researching manufacturer stack ups

If you are concerned with volt spacing, you must also take considerations for multi-layer boards. Not only do you need to consider the spacing between traces on the left and right of a given trace, but you must also consider the spacing the trace and traces on top of, or below it. You'll have to contact the PCB manufacturer in order to find out what these distances are. - Also consider capacitive coupling

Having conductors parallel to one another for a significant length (>5in) can cause a capacitive coupling effect. This will in essence make a*low pass filter*, and if the frequencies of the signals are high, they will be attenuated. Therefore it is a good idea to always minimize the amount of parallel conductors, and also keep as much space between conductors as possible. - How to use tools to calculate

In the PCB Toolkit, go to the "Conductor Spacing" tab. Here you can select the voltage range you expect between conductors, as well as where the trace is located on the board (reference he provided key in the software for what B1, B2, etc. stand for). Note that B1's minimum spacing values are always smaller than B2. This is because it is harder to have an electrical arc travel through epoxy glass than it is for the arc to travel trough air.

- Researching manufacturer stack ups
- Differential, or noise sensitive traces

Noise sensitive traces can get very complex quickly. There are a lot of crazy techniques to "shield traces" or prevent noise from getting into the signal. Here are my tips to handling Noise sensitive traces.- Use differential analog inputs to get rid of common mode noise.
- Keep the two signal traces very close together. That way any noise present will be induced on both traces. Since the signals are differential, the noise will be canceled out.
- Keep your noise sensitive traces far away from any power traces, or anything that is switching. These traces cause a lot of noise, so it's best to be on the other side of the board from them.

- All Net properties should be set
__before__start of design

This is important. Make sure you set all of your net properties*before*you start routing. If you complete routing, and then change properties of the nets, you run the risk of causing a lot of Design Rule Check errors (DRC) (IE if you change a trace width and it now overlaps another trace)

- Trace Width Calculation

**Footprint Design**

Designing custom part footprints can be very tedious if they are not a standard pin package. You can start this process by clicking (at the top of the window) Tools > Part Wizard. Below is an explanation of what's going on in each of the 7 steps for the wizard.- Technology

Here's where you select what type of mounting the part is. Like all of the parameters in footprint design, this information will be found in the part's data sheet.*The Technology Page of the Part Wizard* - Package Type

This step allows you to select some standard package types. The package type of your part should be specified in the data sheet. If you are making a footprint for a part that does not use any of the predefined package types, pick something close to use as a baseline.*The Package Type Page of the Part Wizard* - Package Dimensions

This specifies the dimensions of your part. Once again, reference the data sheet to find out this information. It is always good to use the dot for signifying pin 1 on your part. Though 3D data is needed for your board, it might be useful to visualize air flow across your board, or when/if you export the board design to a 3D file for mechanical engineering packaging.*The Package Dimensions Page of the Part Wizard* - 3D Color Settings

Set the colors of your part to make your rendered 3D model look more accurate.*The 3D Color Settings Page of the Part Wizard* - Pad Type and Dimensions

Typically the only thing you should have to change here is the drill hole diameter (From your datasheet). It's a good idea to keep the pad size as "Use design rules" unless you are having some sort of routing issues and need the pads to be smaller. If you have a part that has multiple different pin sizes, pick the most predominant size here, and we'll add/modify pins later.*The Pad Type and Dimensions Page of the Part Wizard* - Pins

Here is where you set the number of pins on your part. Also set your distances between pins according to the data sheet. If you are using a non-standard package, just set your pin count, and then leave everything at default; we'll change it later.*The Pins Page of the Part Wizard* - Pad Numbering

Name/Number your pins here. If you can't do it how you want in the Part Wizard, you can change pin numbers later manually.*The Pad Numbering Page of the Part Wizard* - Modifying Footprints:

After you've finished with the Part Wizard, your screen will show your designed part. If you're happy with the way it looks, go ahead and save it (File > Save). If you have to make changes, reference some of the following pieces of advice.- Changing Pad Properties/Position:

Right click a pad, and then select "Properties." In the Attributes tab, you can change the pin number. In the General tab, you can change the position of the pad relative to the origin point. This can be useful for fine tuning a pad's location. Also note that you can move the origin to a new point by Design > Set Reference Point. By moving the reference point, you can change a position relative to another pad. The Pad Tab allows you to change the physical dimensions of the selected pad. - Grid Spacing:

You can adjust the grid spacing by clicking Options > PCB Properties > Grid & units. You can adjust the grid step value to make it easy to organize and lay out pads. For example if you have a segment of pins that is spaced 250mil relative to a pin, then set your origin to that pin, and then set your Grid step value to 250mil. It can also be useful to set the value to 0.0000001 to have virtually continuous placement options - 3D Data:

You can turn on the 3D-Info Layer in the Design toolbox, and either edit the existing shape, or add shapes from Place > Shapes.

- Changing Pad Properties/Position:

- Technology

**3D Data and Transfer to Solidworks**

Once and awhile, you might need to include your PCB in a 3D model (Perhaps for designing an enclosure, or some other packaging purpose. To export the 3D model, click File > Export > 3D DXF. Note: when you import it, make sure you set the units correctly.

**Planes**

Planes are large areas of copper that are left after the traces have been cut into the board.- Detrimental if left unconnected

If a plane is left unconnected you might get capacitance-related issues. This is because these planes can build up charges, and not have any way to drain the charge. So always consider having a plane connected to a pin (IE Ground) - Can make routing easier

A very common practice is to connect planes to power distribution pins. For example 5 volts on the top plane, and common on the bottom plane. This can be done by clicking Place > Power Plane. Then select which net you want, and which layer to route the net on.

- Detrimental if left unconnected

**Considerations on Board rigidity**

When designing boards, you should consider how rigid the final product will be. If you have a multi layer board, and you have planes cut out of a common area, you run the risk of the board flexing at that point. Therefore it is a good idea to use planes on every layer. Or at least use planes on the top and bottom layers.

**Part Placement**

When placing parts, it can be useful to adjust the grid spacing, as well move the origin, to position in an organized fashion (See the above section on modifying footprints). Another useful group of tools is Edit > Align. In this menu, there are multiple options to align selected parts, and distribute them equally.

**Routing**- Line tool and its uses

The Line tool can draw a trace anywhere. If you scroll over the end of an existing trace, you can continue drawing from that point. Be careful: The line tool will allow you to draw on top of existing traces, causing DRC errors. You must also use the line tool to connect to a newly place via.*The Line tool Button* - Follow me tool and its uses

The follow me tool will only connect a point on a net to another point on the net. This tool will not allow you to place traces that will cause DRC errors. When routing traces with this tool on long boards, it is best to place point by point in order for optimal placement. Ultiboard's automatic trace placement can be a bit messy.*The Follow Me tool Button* - Via Placement

Vias are used to connect a trace on one layer to a trace on another layer. You can place a via by clicking the Via tool in the top menu. Once you've placed the via, a "Select Lamination for Via" menu will pop up. Always select Copper Top and Copper Bottom, unless you are dealing with some special micro-vias. Keep in mind that each via an through-hole on your board is going to increase manufacturing costs. So it is a good idea to keep the via count to a minimum*The Via Placement tool Button* - Routing Logic
- Ever other layer every other direction principle

It is a good idea to route every other layer predominantly in opposing directions. This is for two reasons. The first reason is to minimize capacitive coupling, or in other words, having closely parallel traces. The second reason is it will make it easier when it comes to using vias and traces to cross over existing traces.*The left two traces are placed to minimize cross over (Good). The right two traces have a lot of cross over (Bad)* - Differential pair routing

Here is some information copied from the above section "Trace Properties"- Keep the two signal traces very close together. That way any noise present will be induced on both traces. Since the signals are differential, the noise will be canceled out.
- Keep your noise sensitive traces far away from any power traces, or anything that is switching. These traces cause a lot of noise, so it's best to be on the other side of the board from them.

- Keep to a side idea

I realize this is contradictory to what was said earlier about keeping distance between traces, but it is also easier for routing if you keep traces tightly clustered. Doing this will give you more open areas to place vias where necessary.*Traces routed tightly together* - Types of corners
- 90 degrees and its detriments

Ultiboard makes it difficult to place 90º angles for a reason. If 90º corners are avoided, traces will be shorter, and therefore resistances and inductances will be lessened. Also 90º traces can be hard to manufacture if using a mill.*A right angle trace (bad) and a chamfered trace (good)* - Avoiding sloppy routing (minimize trace vertices)

Another good practice is to reduce the amount of bends in a trace. The more bends in a trace, the likely a manufacturing error is. Also the board will look better aesthetically if things are kept simple.*A poorly routed trace vs an efficiently routed trace*

- 90 degrees and its detriments
- Copy and pasting routing

When doing a large circuit that contains duplicate sub-circuits, it can be useful to copy and paste routing and placement. To do this you must first either create a part group or net group bu going to Tools > Group Editor. Place and route the group in the desired configuration. Then select the next parts that you want to be placed in the same fashion. Make a group of these parts, and be sure that in the list, parts from the new group are in the same order as the old group. Then go to Design > Group Replica Place or Design > Copy Route.

- Ever other layer every other direction principle
- The Autorouter

It is possible to forgo all routing efforts by clicking Autoroute > Start/resume Autorouter. In simple boards this process should occur pretty quickly. Go through all the traces and clean them up, because I guarantee that there are unneeded bends. In order to use Autorouting well, it is assumed that you have all of the Net Properties set up correctly. Also be sure to set every other layer to be perpendicular at Options > PCB Properties > Copper Layers > Copper Layer Properties. For complex boards, the Autorouter will take a long time, and sometimes may not converge on a solution. This does not mean the board is impossible to make, it only signifies that a human touch (and logic) is required to make the remaining connections.

I don't use the autorouter, because I feel that I can do a much better job logically routing traces. Don't let robots take your jobs, people.

- Line tool and its uses

**Design Rule Check (DRC)**

While designing a PCB, it is inevitable for you to run into DRC errors. The most common errors you will run into are traces being to close to one another, vias being to close to something, something not connected, or something is incorrectly connected. These are represented by little red circles on the board design. You can go to each individual error by Clicking (at the bottom) DRC, and then click an error to go to that spot on the board. To recheck for errors, click Design > DRC and Netlist Check. If your board is left with erros when you send it out

**Net List editor**

Sometimes it is nessisary to add components or connections on the Ultiboard file. This can be done by entering Tools > Netlist Editor. Nets can be added, renamed, and connections can be added in this menu.*The Netlist Editor*

**Finalizing designs**

Congratulations. You've finished your design and are ready to send it out to a manufacturer. PCB manufacturers make your boards from Gerber files, not Ultiboard files. To create Gerber files, go to File > Export. I typically generate a gerber file for every option, however a manufacturer may not require all of them. Talk to your manufacturer and ask them what they require, but note that they typically won't mind if you send them more than they need (And they'll be sure to let you know if you didn't send enough). It is also typically a good idea to oversize your soldermasks by at least 1 mil. This will make your boards easier to solder to.*The File Export Window*

**Revisions**

It may be nessisary to make changes to your design. If you've generated a forward annotation file by making changes in Multisim, go to Ultiboard, and click Transfer > Forward annotate from file. If you are making change to a board file and want to send the changes to Multisim, click Transfer > Backwards annotate to Multisim > Backward annotate to Multisim 13.0

**Problem Statement:**

Let's say you're playing a game where someone rolls a 6 sided die and then reports the number rolled. The opponent may lie - and if you can guess when he lies, you win. Since this game is for money, you've done the due preparations and collected the following data:

- The other player lies 20% of the time
- The die was cooked in an oven and is weighted to land with a 6 up, giving you the following probabilities:
- $P(R=1)=.05$
- $P(R=2)=.20$
- $P(R=3)=.20$
- $P(R=4)=.15$
- $P(R=5)=.15$
- $P(R=6)=.25$

Alright, it's game day, you're sitting at the table, and sweat is running down your brow. You've placed 25,000 dollars on this bet because you suffer from a gambling addiction. The opponent rolls the die, looks up, and says, "3." What is the probability that the roll is really 3?

**Solution:**

Be careful - it may be tempting to assume that the answer is 20%, because that's how often they lie. But that is not correct - we must also consider the probability that a 3 would be rolled at all (Plus pro-tip to students, if information is given on a test, you probably need to utilize it). It is valuable to first draw a diagram to understand the probability distribution:

The probabilities used in the diagram are derived from the probability of a lie. The truth can only be a 3 was rolled, and he reported a 3. You know no information on how he may lie, so assume that he randomly selects alternate values at an equal probability. Therefore the 20% is divided across the 5 answers which are lies. This tool will help us answer the question, which can be mathematically stated as;

$$P(R_P=3|R_R=3)$$

Where $R_P$ is the potential roll, and $R_R$ is the roll reported. To get some guidance on what to do next, let's put this in Bayes theorem form;

$$P(R_P=3|R_R=3) = \frac{P(R_R=3|R_P=3)P(R_P=3)}{P(R_R=3)}$$

The first term, $P(R_R=3|R_P=3)$ can be found from our little diagram. Read it as, "Given the potential roll was a 3, what is the probability the reported roll will be a 3?" Just look at the link between $R=3$ and $R=3$ to see that the probability is 0.8

The second term, $P(R_P=3)$, can be found from the problem statement. This is just the probability that a 3 would be rolled. Therefore this term is 0.2.

The bottom term is a little vexing when you think about it. What is the probability that the reported value, $R_R$ is 3? Here is where the law of total probability comes in. Here we simply take the sum of all the probabilities for $R_P$ multiplied by their connections in the diagram.

$$P(R_R=3)=P(R_R=3|R_P=1)*P(R_P=1)+P(R_R=3|R_P=2)*P(R_P=2)+P(R_R=3|R_P=3)*P(R_P=3)+P(R_R=3|R_P=4)*P(R_P=4)+P(R_R=3|R_P=5)*P(R_P=5)+P(R_R=3|R_P=6)*P(R_P=6)$$

Substituting values we get:

$$P(R_R=3)=0.04*0.05+0.04*0.20+0.80*0.20+0.04*0.15+0.04*0.15+0.04*0.25=0.192$$

There we go now we just need to plug the values into our Bayes Theorem Equation:

$$P(R_P=3|R_R=3) = \frac{0.8*0.2}{0.192}=0.8333$$

So what does this number mean? In our equation, we were asking "What is the probability that the opponent reported exactly what was rolled?" There is an 83% chance that he is telling the truth. So this guy's a moron! If he would have lied more when you were stalking him, you would have had much less certainty. Or perhaps your data is flawed because your opponent knew you were watching so he acted differently. Bottom line: don't gamble kids - invest in a sturdy mutual fund.

All joking aside, you can do a quick sanity check before letting this be your final answer. If the ONLY information you had was that he lies 20% of the time, then you know that he speaks the truth 80% of the time. But when ever you condition this on other information, your certainty will always increase. So if the number is smaller than 0.8, we have a problem.

**Problem Statement:**

You won your previous bet thanks to your knowhow of statistics and you're feeling pretty confident. So naturally you go to the black jack tables. First hand you're dealt a 10 and then a 5. If you hit (receive another card) what is the probability that you will bust? (surpass 21). For those not familiar with blackjack, you'll need to know the following

- Face cards are all worth 10
- Aces can be 1 or 11. But selecting an 11 in this case would result in a bust
- Assume you have no knowledge of the cards left in the deck (counting cards is a good way to get the crap beat out of you in a back alley by casino staff)

**Solution:**

This is a fairly simple computation problem. All that must be done is add up the probabilities of each card that will put you past 21. Namely, 7,8,9,10, and any face cards. There are 14 total cards (1-10, J, K, Q, A). So there are 7 out of 14 cards that will bust or exactly 50%. So there you go - if you ever have a hand of 15 in blackjack, you know that you walk a very fine line between a high hand and busting - with no certainty either way.

**Problem Statement 1:**

Let's say you just got done cooking some food to bring to a pot luck. You had to cook the food in a pot at 200C. You turn the pot off and run out the door. You'll be gone for exactly 20 minutes. And you know that your cat always jumps up on the counter and walks around once while you're gone. What is the probability that your cat will burn her cute little kitty paws? Some things you should know:

- The temperature is defined by an exponential decreasing function, where $T$ is temp and $t$ is time (in minutes): $$T=(200-27)*e^{-.5t}+27$$
- Burns can be caused at 44C or higher.

**Solution 1:**

When the cat jumps on the stove is a random uniform variable with a range from $t=0$ to $t=20$. And here's the point where I realize this problem is too simple. All I have to do is find the amount of time that the cat could get burned and divide it by the amount of time total. Back calculate from the given temperature equation to find that when $T=44$, $t=33$. Using Sage Math:

```
f(t)=(200-27)*e^(-.25*t)+27
solve(f(t)==44,t)[0].rhs().n()
plot(f(t),(t,0,50),ymin=0)
```

We find that the time when the stove is okay to walk on is at 9.28 minutes. That means the probability is simply $9.28/20$ which equates to a 46.4% chance. Oh no that's far too unsafe! Don't leave your cat unattended in these conditions - the potluck can wait. As a quick sanity check, analyze the plot of the function

That said, this problem was written on the fly, and was kind of boring. So let's come up with one akin to this with a bit more complexity.

**Problem Statement 2:**

You've set up a hidden camera and have observed that your cat only jumps up on the counter near when she expects you to arrive. You've found the pdf to be:

$$P_J(t)=k(e^{0.1t}-1)$$

$k$ is a constant that will depend on the amount of time you are gone. Given the scenario from the previous problem, what is the probability your cat might burn her little paws?

**Solution 2:**

First let us define $P_J(t)$ for this specific problem. We must solve for $k$ using Sage Mathematics:

```
var('k')
PJ(t)=k*(e^(.1*t)-1)
Knew=solve(integral(PJ(t),(t,0,20))==1,k)[0].rhs().n()
```

$k$ is found to be 0.0228 for this problem. As a quick sanity check, validate that the PDF with the a substituted value of K integrated over the range is equal to 1.

`integrate(PJ(t,k=Knew),(t,0,20))`

Now that we have the PDF we can find the probability that the cat may get burned to do this, integrate the PDF from $t=0$ to $t=9.28$ (this value for $t$ was found in the previous problem):

`integrate(PJ(t,k=Knew),(t,0,9.28))`

The probability is found to be 13.7%. Phew that is a lot more comfortable than the previous statement.

**Problem Statement 3:**

Your wife still doesn't like those odds and wants to train the kitty to stop jumping on the counter entirely. So let's say she's going to hide in the bathroom while you leave (once again for 20 minutes). Your wife only has one shot to catch your cat in the act (Otherwise your cat will obviously know she's there). When is the best time for your wife to try and catch your cat in the act?

**Solution 3:**

In order to calculate this, we must calculate the expected value of when they will jump or $E[j]$. To calculate expected value, you must use the following equation:

$$E[x]=\int^{\infty}_{-\infty}xf_X(x)dx$$

So for our application:

$$E[j]=\int^{20}_{0}tP_J(t)dt$$

Using some of the Sage Math work from before, we can find this value:

`integrate(t*PJ(t,k=Knew),(t,0,20)).n()`

And this value is 14.55. So at $t=14.55$ your wife should check on the kitty. This may not be the most valid solution to the originally asked question when you really think about it however. Should you check at the expected value, or when the pdf is at the highest probability $t=20$?

**Problem Statement:**

Suppose you have an electrode generating an arc used for welding. The arc will contact the target substrate on the x axis according to a Gaussian random variable with a mean of 0 (the position is relative to the electrode). You have found a clever way to control the standard deviation of the arc by introducing a solenoid to "guide" the arc. Adjusting the current through the solenoid will proportionally decrease the standard deviation according to the simple equation:

$$\sigma=10-0.1I$$

A few things to note about this equation, if there is no current through the solenoid, the standard deviation is 10mm. If the current is 100A, then the standard deviation is 0 (which is not possible). So this model is slightly broken, but will still suit this question.

You want 95% of the arc pulses to fall within a rand of -0.5mm to 0.5mm, and want to use as little current as possible (to avoid paying for a high current supply, as minimize heat generated by the solenoid). How much current do you need?

**Solution****:**

Let us jump right to the CDF of the function (found from Wikipedia):

$$F_X(x)=\frac{1}{2}[1+erf(\frac{x}{\sigma{\sqrt{2}}})]$$

Now we can set up an equation to solve for $\sigma$

$$0.95=F_X(0.5)-F_X(-0.5)$$

This can be solved in Sage Math

```
var('s',latex_name='\\sigma')
FX(x)=0.5*(1+erf(x/(s*sqrt(2))))
solve(0.95==FX(.5)-FX(-.5),s)
```

And the solution is:

$$\frac{\sqrt{2}}{4*erf^{-1}(\frac{19}{20})}$$

By default, sigma does not have an inverse error function. So use the following script to find a numerical approximation we find our standard deviation is 0.255

```
import scipy.special as st
n(sqrt(2)/(4*st.erfinv(19/20)))
```

Now how can we be sure if this is really correct? Let's run a quick simulation in Octave GNU. We'll run 1,000,000 trials, and then find how many of the values are between -0.5 and 0.5.

`X=normrnd(0,0.255106728462327, 1,1E7); mean(-0.5<=X & X<=0.5); hist(X,30)`

We get a value of 0.95003. Running the test a few more times, it stays pretty close to 0.95, so we know we didn't just get lucky. This script also generates a plot:

It's pretty easy to convince yourself with this plot that 95% of the samples are between the limits of -0.5 and 0.5.

The resistor ladder is a simple to build circuit that functions as a digital to analog converter (DAC). So what are DACs used for? Well the most common use is audio generation. The media files on your phone (or iPod, MP3 player, what have you) are stored digitally on the devices memory. When the music is played, the microprocessor in the device outputs a string of bits to the DAC. That string of bits represents the amplitude of sound at a specific point in time. Now you headphones don't work off binary; they need varying voltages in order to make sound. This is where the DAC comes in; it's purpose is to systematically convert the binary value into a voltage value that can then drive the speaker.

Just like audio, video signals can be represented as binary values, so DACs are used for that as well. However that is becoming a rare thing with the advent of technology like HDMI, which send signals in a completely digital manner.

Now, why did I choose to write about resistor ladders, rather than DACs as a whole? Well, the cool thing about resistor ladders, is they are simple in every aspect. Simple to build. Simple to interface with. Simple to do circuit analysis with. There are a few drawbacks which we'll get to later, but first let's take a look at how the circuit works.

The resistor ladder works by dividing the input voltage at each bit by a certain ratio, such that the smallest bit (the least significant bit or LSB) changes the output very little, and the largest bit (the most significant bit (MSB)) effects the output the greatest. The anatomy of the circuit is fairly simple, and can be seen below. Note that any value of resistors can be used as long as the 2R resistors are twice as large as the R resistors. The configuration can expand for any number of bits. It also should be noted that as resoluton increases (more bits), you're going to want hire accuracy resistors, otherwise it may not operate linearly.

Let's take a look at the lowest resolution resistor ladder possible; a single bit. The analysis for this circuit is pretty simple, if the *B0* is off, there is no current through the circuit, and therefore the output will be 0 volts. When *B0* is on, or at 5V, the circuit is acting as a voltage divider, and will follow the standard equation:

$$\small{OUTPUT = 5V*\frac{2R}{2R+2R} = 2.5V}$$

Anything seem weird here? What good is this doing? Well, to be honest it's not a very good DAC right now, because it is at a *very low resolution*. In fact it's as low as you can go. One thing to take note of in this example however, is that the circuit does not output the full "swing" of the possible voltage. Meaning, you'd like your signal to be able to range from 0V to 5V, but it's falling short. This is a problem that comes up with this DAC regardless of resolution. However, as resolution increases, the max output of the DAC approaches the supply voltage asymptotically.

Digital Input | Output |
---|---|

B0=0 | 0V |

B0=1 | 2.5V |

Let's look at the next step up in resolution: 2 bits. The circuit analysis becomes a bit more difficult, but nothing too extreme. Let's look at all of the cases.

**Input = "00**_{b}"

When the input is 00_{b }or simply "0", there is no current flowing through the circuit, and therefore no voltages present at any point. The Output would be equal to 0V.**Input = "01**_{b}"

When the input is a decimal value of 1,*B0*is at 5V and*B1*is at 0V or GND. Since*B1*is at GND, the 2R and R resistor connected to it are now in parallel with the 2R resistor connecting to the GND reference. We can find the voltage ($V_A$) at the end of the*B0*2R resistor:

$$\small{V_A= 5V *\frac{2R||(R+2R)}{2R+2R||(R + 2R)} =1.875V}$$

This is not yet the end result as the 1.875V at $V_A$ is now divided across an R and 2R resistor. We apply the voltage divider equation to get the output

$$\small{OUTPUT = 1.875*\frac{2R}{R + 2R} = 1.25V}$$**Input = "10**_{b}"

For a decimal input of 2,*B0*is 0V, and*B1*is at 5V. The 2R resistor connection to*B0*and the 2R resistor connecting to GND are in parallel, turning this problem into a voltage divider problem to find the output:

$$\small{OUTPUT = 5V*\frac{R+2R||2R}{2R + R+2R||2R} = 2.5V}$$**Input = "11**_{b}"

Lastly for a decimal input of 3, both*B0*and*B1*is at 5V. We can apply a similar trick as we did for an input of "1." The 2R and R resistor connected to*B1*are in parallel to the 2R resistor connected to*B0*. So we can find the voltage ($V_A$) at the 2R resistor connecting to GND by the following Equation:

$$\small{V_A=5V*\frac{2R}{(2R+R)||2R + 2R)} = 3.125V}$$

Now to get the output, we know the voltage across*B1*'s 2R resistor and the R resistor must equal 5V-3.125V, or 1.875V. To get the output, Now taking that voltage across the divider made by 2R and R, we get 0.625V. Adding this to it's reference of 3.125V yields the output as 3.75V.

Binary Input | Decimal Input | Voltage Output |
---|---|---|

00 | 0 | 0V |

01 | 1 | 1.25V |

10 | 2 | 2.5V |

11 | 3 | 3.75V |

There's definitely a trend going on here. Despite the fact that the analysis steps were pretty different for each configuration, we see that each time the input increases by "1", the voltage increases by 1.25V. This is a linear relationship, that is modeled by a standard equation:

$$\small{V_{out}=IN_B*\frac{V_{ref}}{2^N}}$$

Where $IN_B$ is the value of the binary input, $V_{ref}$ is your logic level (I used 5V for all of the examples), and $N$ is the the bit resolution of the resistor ladder.

Notice our maximum voltage output (3.75V) got closer than the 1 bit DAC's maximum (2.5V) to the absolute maximum ot 5V. This is a known problem that one must deal with in the circuit. The other problem is that the circuit cannot directly be connected to a load. If it is, the resistance of the load will throw off the balance of the circuit, causing faulty operation. This can be fixed fairly simply, by hooking the circuit's output to some sort of voltage follower amplifier (Be it a transistor, or an op-amp). The last problem that all DACs have at their route level is that the voltage levels are *discrete*. This means that as the voltage is changes, it does no do so in a strait line. Instead it must increase in steps, as seen in the figure below. This problem can be solved by some simple filtering

The above video is a simplified look at operational amplifiers and the many uses they have. A quick example is shown, and a few practical pieces of advice are given.

- Download Qucs Simulation Package HERE
- Simulation files from this video: DC Analysis & Transient Analysis
- Op-Amp Circuit Reference Document
- Standard Resistor Values
- My Public Notes on Op-Amps

The above video is a simple demonstration on how easy it can be to design a __useful__ 3D printed part. The design is done in OpenSCAD. Click HERE for the OpenSCAD cheat sheet I reference.

The OpenSCAD script and STLs 3D files can be found HERE on Thingiverse.

**PERCH DESIGN SCRIPT:**

```
difference(){
cube([80,70,15]);
translate([10,0,0]){
cube([60,60,15]);
}
}
difference(){
translate([-5,0,-12.5]){
cube([90,10,40]);
}
difference(){
cube([80,70,15]);
translate([10,0,0]){
cube([60,60,15]);
}
}
}
```

How Tensioning works in the Open Source Ecology D3D construction set. This brief video describes both installing the belt, and removing the belt